Topic: Digital Circuits
In a 4-bit ripple counter using JK flip-flops, the maximum frequency of input clock is limited due to:
- A. Propagation delay
- B. Setup time
- C. Hold time
- D. Fan-in
Answer: A. Propagation delay
Explanation: In an asynchronous (ripple) counter, the clock input of each subsequent flip-flop is triggered by the output of the preceding one. Consequently, the propagation delay of each flip-flop accumulates. For an $n$-bit counter with flip-flop delay $t_{pd}$, the total settling time is $n imes t_{pd}$. To ensure reliable operation, the clock period $T_{clk}$ must be greater than this cumulative delay, directly limiting the maximum operating frequency ($f_{max} \le 1/(n \cdot t_{pd})$).