Topic: Digital Circuits
Which of the following operator cannot be synthesized by VHDL synthesis tools?
- A. +
- B. -
- C. *
- D. &
Answer: C. *
Explanation: No option is right. These all operators are used in VHDL (+ Addition, - Subtraction, * Multiplication, & Concatenation). Note: The source key indicates an error in the question options.