Topic: Digital Circuits
The Above Verilog/ VHDL module depicts which sequential element:
- A. Rising edge Flip-flop with synchronous Reset
- B. Falling edge Flip-Flop with synchronous Reset
- C. Rising edge Flip-flop with asynchronous Reset
- D. Falling edge Flip-Flop with asynchronous Reset
Answer: A. Rising edge Flip-flop with synchronous Reset
Explanation: In both the VHDL and Verilog snippets, the process block triggers exclusively on the rising edge of the clock (`if (clk'event and clk='1')` and `always @(posedge clk)`). Inside this synchronous block, the reset condition is checked. Since the reset is evaluated only on the clock edge, it is a synchronous reset. Therefore, it models a rising edge flip-flop with a synchronous reset.