Topic: Digital Circuits
Which of the following is not true in VHDL?
- A. Signal assignment can be used inside a FUNCTION
- B. In an ENTITY, all PORTS are SIGNALS by default
- C. (CLK'EVENT and CLK='1') can be used to describe the rising edge event of CLK signal
- D. std_logic data type can assume a maximum of 3 types of values
Answer: A. Signal assignment can be used inside a FUNCTION
Explanation: In VHDL, functions execute in zero simulation time and cannot have side effects. Therefore, they are not allowed to contain signal assignment statements (<=); they must use variable assignments (:=) instead. Note that option (d) is also technically false since the IEEE 1164 standard `std_logic` has 9 states (U, X, 0, 1, Z, W, L, H, -), not 3. However, (a) is commonly accepted as the primary syntax rule violation in such context.