Topic: Digital Circuits
High State noise margin of standard TTL and 5V CMOS logic gate are
- A. 0.4V, 0.4V
- B. 0.4V, 1V
- C. 1V, 0.4V
- D. 1V, 1V
Answer: B. 0.4V, 1V
Explanation: For standard 5V TTL logic, the minimum high output voltage $V_{OH(min)}$ is 2.4V and the minimum high input voltage $V_{IH(min)}$ is 2.0V. The High State noise margin is $NM_H = V_{OH(min)} - V_{IH(min)} = 2.4V - 2.0V = 0.4V$. For standard 5V CMOS (like the 74HC series), the values are typically $V_{OH(min)} = 4.4V$ or 4.9V and $V_{IH(min)} = 3.5V$, yielding a typical high state noise margin around 1V to 1.4V. Thus, 0.4V and 1V are the standard textbook values respectively.