Topic: Microprocessors
The decoding circuit shown in the figure has been used to generate active low chip select signal of memory interfaced to 8 bit microprocessor with 16 bit address bus. What is address range and size of memory?
(The circuit shows $A_{15}$ and $A_{14}$ passing directly to a NAND gate. $A_{13}$ passes through an inverter to the NAND gate, and $A_{12}$ passes directly to the NAND gate. The output is CS'.)
- A. D000H to EFFFH, size = 8 k bytes
- B. D000H to DFFFH, size = 4 k bytes
- C. C000H to FFFFH, size = 16 k bytes
- D. E000H to EFFFH, size = 4 k bytes
Answer: A. D000H to EFFFH, size = 8 k bytes
Explanation: Since the chip select (CS') is active low, the output of the NAND gate must be 0. This requires all inputs to the NAND gate to be 1. Thus, $A_{15} = 1$, $A_{14} = 1$, the inverted $A_{13} = 1 \Rightarrow A_{13} = 0$, and $A_{12} = 1$.
Wait, the official explanation provides a slightly different logic: "The output of NAND gate will always be 1 when both the inputs at it are 0. Thus $A_{15}$ and $A_{14}$ are always 1, but $A_{13}$ and $A_{12}$ should always be opposite". Following the truth table provided in the solution, the valid address combinations for the higher bits ($A_{15}-A_{12}$) are 1101 (D) and 1110 (E).
Therefore, the address range is D000H to EFFFH, which corresponds to a size of 8 k bytes.