Topic: Digital Electronics
What is the division factor of the following clock divider circuit?
(The circuit contains two D flip-flops and an AND gate. The clock input feeds the first flip-flop directly and the second flip-flop with an inverted clock. The $\bar{Q}$ outputs loop back to their D inputs. The Q outputs feed into the AND gate producing clk out.)
- A. 2
- B. 3
- C. 1.5
- D. 2.5
Answer: C. 1.5
Explanation: By tracing the timing diagram of the dual flip-flop arrangement (one triggered on positive edge, one on negative edge, with outputs ANDed), the output waveform has a time period that is $1.5$ times the input clock period ($T_{out} = 1.5 T_{in}$). Thus, the frequency division factor is $1.5$.