Topic: Electronics Engineering
Consider the following assembly code for a hypothetical RISC processor with a 4-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).
add r1, r2, r3 // $r1=r2+r3$
sub r4, r1, r3 // $r4=r1-r3$
mul r5, r2, r3 // $r5=r2^{*}r3$
Identify the possible pipeline hazard and the affected instruction.
- A. Read after write hazard during mul
- B. Read after write hazard during sub
- C. Read after write hazard during add
- D. Write after write hazard during mul
Answer: B. Read after write hazard during sub
Explanation: Here r1 is written in the $4^{th}$ cycle of the 'add' instruction, while before writing, the 'sub' instruction is going to read r1 in its $3^{rd}$ cycle. So this is a read after write hazard.