ISRO Electronics & Communication (ECE) 2007 - Question 18

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For one of the following conditions, clocked J-K flip-flop can be used as DIVIDE BY 2 circuit where the pulse train to be divided is applied at clock input

  • A. J=1, K=1 and the flip-flop should have active HIGH inputs
  • B. J=1, K=1 and the flip-flop should have active LOW inputs
  • C. J=0, K=0 and the flip-flop should have active HIGH inputs
  • D. J=1, K=1 and the flip-flop should be a negative edge triggered one

Answer: D. J=1, K=1 and the flip-flop should be a negative edge triggered one

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