Topic: Digital Logic
Which of the following options is not true for a gated D-type flip-flop?
- A. when clock is high, allows the input data (D) to pass through to the output (Q)
- B. stores a single bit of data
- C. uses a clock signal to control when the input data (D) is transferred to the output (Q)
- D. when clock is low, allows the input data (D) to pass through to the output (Q)
Answer: D. when clock is low, allows the input data (D) to pass through to the output (Q)
Explanation: A gated D-latch (often casually referred to as a level-triggered D-type flip-flop) allows data to pass from input D to output Q when the enable/clock signal is HIGH (transparent state). When the clock signal is LOW, the latch is in the hold/opaque state, meaning it stores the previous value and ignores any changes at the D input. Therefore, option (d) is false.