Topic: Digital Logic / VHDL
In VHDL simulation, consider the following process:
```vhdl
signal A, B: std_logic :='0';
process
begin
A<='1';
B<=A;
wait;
end process;
```
What will be the value of signal B immediately after simulation starts?
- A. '1'
- B. '0'
- C. 'U' (undefined)
- D. Z
Answer: B. '0'
Explanation: In VHDL, signal assignments using `<=` inside a process are not updated immediately; they are scheduled to be updated at the end of the current simulation delta cycle. When `B<=A;` evaluates, signal `A` has not yet changed to '1' and still holds its initial value '0'. Thus, B gets assigned '0', and the process then suspends at the `wait;` statement.