Topic: Electronics Engineering
What is the maximum clock frequency at which following circuit can be operated without timing violations? Assume that the Combinational logic delay is 10 ns and the clock duty cycle varies from 40% to 60%
- A. 100 MHz
- B. 50 MHz
- C. 40 MHz
- D. 25 MHz
Answer: C. 40 MHz
Explanation: FF(2) is negative edge triggered it should not change its output until and unless the output of FF(1) does not reach at its input via combinational logic. Output to FF(1) takes 10 ns to reach at the input of FF(2). During this 10 ns time, FF(2) should not change its value. (-)ve edge of clock should come after 10 ns. $40\%$ of $T = 10~ns \Rightarrow \frac{40}{100} \times T = 10~ns \Rightarrow T = 25~ns$. $f = \frac{1}{T} = \frac{1}{25\times10^{-9}} = 40~MHz$. $f_{max} = 40~MHz$. Note: In question, it is asked for maximum clock frequency. So 40% of duty cycle is taken for calculation.