ISRO Electronics & Communication (ECE) 2009 - Question 51

All ISRO Electronics & Communication (ECE) papers | ISRO Electronics & Communication (ECE) 2009

Topic: Electronics Engineering

Which is the correct order of different process steps for a typical FPGA design?

  • A. Functional simulation, Synthesis, Place & Route, Timing Verification
  • B. Functional simulation, Timing Verification, Synthesis, Place & Route
  • C. Timing Verification, Synthesis, Functional simulation, Place & Route
  • D. Synthesis, Functional simulation, Timing Verification, Place & Route

Answer: B. Functional simulation, Timing Verification, Synthesis, Place & Route

Explanation: Detailed standard solution.

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