The sum S of A and B in a half adder can be implemented by using K NAND gates. The value of K is
- A. 3
- B. 4
- C. 5
- D. None of these
Answer: B. 4
Explanation: A half adder's sum output is represented by the XOR operation ($A \oplus B$). Implementing a 2-input XOR gate using exclusively 2-input NAND gates requires a minimum of 4 NAND gates.