A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1 $\mu$sec and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5 V. The leakage current of the circuit should be less than \n\n[Figure needs to be uploaded later]
- A. 2.5 mA
- B. 0.25 mA
- C. 25.0 $\mu$A
- D. 2.5 $\mu$A
Answer: D. 2.5 $\mu$A
Explanation: [Figure needs to be uploaded later]\n$Q=CV=0.1\times 10^{-9}\times 5=5\times 10^{-10}$ C.\n0.5% of $Q = 5\times 10^{-10}\times \frac{0.5}{100} = 2.5\times 10^{-12}$ C.\n$i = \frac{\Delta Q}{\Delta t} = \frac{2.5\times 10^{-12}}{1\times 10^{-6}} = 2.5~\mu A$.