ISRO Computer Science (CSE) 2023 - Question 36

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Topic: Digital Logic

The time delay obtained through an 8 bit serial register with 400 MHz clock is:

  • A. 20 ns
  • B. 2.5 $\mu$s
  • C. 20 $\mu$s
  • D. 2.5 ns

Answer: A. 20 ns

Explanation: The clock frequency is $400$ MHz, so the clock period $T = 1 / (400 \times 10^{6})$ seconds $= 2.5$ ns. An 8-bit serial register requires 8 clock cycles for a bit to pass through. Thus, total delay $= 8 \times 2.5$ ns $= 20$ ns.

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