Consider a pipelined processor with the following four stages... Operand forwarding is used... Number of clock cycles for 3 instructions (ADD, MUL, SUB)?
- A. 7
- B. 8
- C. 10
- D. 14
Answer: B. 8
Explanation: With operand forwarding, stalls are minimized. ADD (1 cycle exec), MUL (3 cycles exec), SUB (1 cycle). MUL depends on ADD (no stall with forwarding). SUB depends on MUL (stall until MUL finishes). Timeline analysis yields 8 cycles.