Topic: Digital Circuits
If Sys clock frequency is > 4 * clk_ext frequency. What is the functionality of above circuit? (Circuit shows D1 clocking clk_ext on Sys Clock, passing to D2, then D3. Output $Q_{out}$ is AND of Q2 and NOT(Q3))
- A. Falling Edge detector with Pulse width of $Q_{out}=$ one cycle of Sys clk
- B. Rising Edge detector with Pulse width of $Q_{out}=$ one cycle of Sys clk
- C. Falling Edge detector with Pulse width of $Q_{out}=$ one cycle of clk_ext
- D. Rising Edge detector with Pulse width of $Q_{out}=$ one cycle of clk_ext
Answer: B. Rising Edge detector with Pulse width of $Q_{out}=$ one cycle of Sys clk
Explanation: The first flip-flop (D1) synchronizes the asynchronous `clk_ext` to the system clock. D2 and D3 act as a two-stage shift register. The AND gate has inputs Q2 and NOT(Q3). The output is high only when Q2 is 1 (current state is high) and Q3 is 0 (previous state was low). This combination perfectly detects a 0-to-1 transition (rising edge) of the synchronized input. Since the shift register is driven by `Sys Clock`, the detected condition lasts for exactly one cycle of `Sys Clock`.