Topic: Digital Circuits
Consider a shift register where the frequency of input signal x is $f_s$ and the shift register is clocked at the positive edge of $2f_s$. The time offset between the output A (after the 1st stage) and output B (after the 3rd stage) is
- A. $1/(2f_s)$
- B. $1/f_s$
- C. $3/(2f_s)$
- D. $1/(4f_s)$
Answer: B. $1/f_s$
Explanation: The clock frequency is $2f_s$, which means the time period of one clock cycle is $T_{clk} = 1/(2f_s)$. Data reaches output A after 1 clock cycle ($T_{clk}$) and reaches output B after 3 clock cycles ($3T_{clk}$). The time offset between A and B is $3T_{clk} - T_{clk} = 2T_{clk} = 2 \times 1/(2f_s) = 1/f_s$.