Topic: Digital Electronics
What is the frequency and duty cycle of output Y, when clk frequency is 1 MHz @ 50% duty cycle?
(The circuit shows a Johnson counter formed by 2 D-flip-flops, where $\overline{Q}_2$ feeds $D_1$, and $Q_1$ feeds $D_2$. The output Y is the AND of $Q_1$ and $\overline{Q}_2$.)
- A. 500 kHz @ 50% duty cycle
- B. 500 kHz @ 25% duty cycle
- C. 250 kHz @ 50% duty cycle
- D. 250 kHz @ 25% duty cycle
Answer: B. 500 kHz @ 25% duty cycle
Explanation: Assuming initially both flip-flops are 0 ($Q_1=0, Q_2=0$), the sequence of states ($Q_1Q_2$) is 00 -> 10 -> 11 -> 01 -> 00.
The output Y is $Q_1 \cdot \overline{Q}_2$.
For 00, Y=0. For 10, Y=1. For 11, Y=0. For 01, Y=0.
According to the official ISRO key and explanation, the output time period is taken as twice the input clock (despite a full 4-state cycle generating one pulse, the official solution asserts "Output frequency = 500 kHz, Duty cycle = 1/4 = 25%"). The answer key records (b).