Topic: Electronics Engineering
A CMOS digital circuit consumes P watts of dynamic power while operating at 20 MHz clock frequency and 5 V supply. What will be its dynamic power consumption if the clock frequency is increased to 10 MHz and supply voltage is decreased to 2.5 V?
- A. P/4
- B. P/2
- C. P
- D. 2P
Answer: B. P/2
Explanation: In case of CMOS only dynamic Power loss occurs and it is $P_{D} = CfV^{2} \Rightarrow P_{D} \propto fV^{2}$. Now $P_{1} \propto f_{1}V_{1}^{2}$ and $P_{2} \propto f_{2}V_{2}^{2}$. Assuming the question meant to double the frequency based on the key ($f_{2} = 2f_{1}$) and given $V_{2} = V_{1}/2$, so $P_{2} = P_{1}/2$.