ISRO Electrical Engineering (EE) 2018 - Question 7

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In the system shown below, what is steady state error in unit ramp response? [Figure description: A block diagram. R(s) enters a summing junction (+ at input, - at feedback) followed by a forward block 1/(s^2 (s+12)) giving C(s). The output C(s) is fed back through three parallel feedback paths that are summed: a block 5(s+1)/(s+5), a block +1, and a block -1, all returning to the negative input of the summing junction.]

  • A. 5/4
  • B. 4/5
  • C. 3/5
  • D. 5/5

Answer: B. 4/5

Explanation: Feedback H(s) = 5(s+1)/(s+5); error E = R − C. For a unit ramp input ess = lim s→0 (1/s)[1 + G(H−1)]/(1 + GH) = 12/15 = 4/5.

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