If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\text{ K} \times 4$ bits?
- A. 13
- B. 15
- C. 16
- D. 17
Answer: D. 17
Explanation: Total memory size calculation:\nArray is 4 rows $\times$ 6 cols.\nEach row has $6 \times 4$ bits = 24 bits width? No, normally chips are combined to form word width or depth.\nAssume '4 x 6 array' means 4 banks of 6 chips? Or 24 chips total.\nLet's deduce from capacity. Each chip $8\text{ K} \times 4$ bits.\nCommon config: form a byte addressable memory.\nTotal capacity: If rows increase depth and cols increase width?\nIf we assume it forms a memory system. Let's look at total bits: $4 \times 6 \times 8\text{ K} \times 4 = 768\text{ K}$ bits = $96\text{ KB}$.\nTo address 96 KB: $2^{16} = 64\text{ K}$, $2^{17} = 128\text{ K}$.\nSo 17 bits are needed.\nDetailed: $8\text{ K}$ needs 13 lines. $4 \times 6$ array suggests expansion. If rows expand words (depth), we need $\log_2(4) = 2$ more lines? Total 15? If chips are $8\text{ K} \times 4$, to get bytes (8-bits), we pair 2 chips. $6$ cols means 3 pairs? $4$ rows means depth $4 \times 8\text{ K} = 32\text{ K}$. $32\text{ K}$ bytes. $32\text{ K} = 2^{15}$.\nLet's check ISRO Solution logic (from similar papers): Total capacity = $4 \times 6 \times 8\text{ K} \times 4$ bits? \nInterpretation: A $4 \times 6$ array likely means increasing word size and depth. \nUsually: Rows $\times$ Capacity/chip. \nLet's calculate total bytes: $4 \times 6 \times 8 \times 1024 \times 4$ bits / 8 = $98304$ bytes. $\ln(98304)/\ln(2) = 16.58$. Needs 17 bits.