Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.
- A. 0
- B. 1
- C. 2
- D. 3
Answer: C. 2
Explanation: CPU frequency = 33 MHz. Cycle time $T = 1/33 \text{ MHz} \approx 30.3$ ns.\nRequired time = Memory access time + Delay = $60 + 10 = 70$ ns.\nNumber of cycles required = $70 / 30.3 \approx 2.31$ cycles.\nSince access must complete, we need 3 cycles total.\nWait states = Total cycles - 1 (ideal) = $3 - 1 = 2$.