ISRO Computer Science (CSE) 2008 - Question 19

All ISRO Computer Science (CSE) papers | ISRO Computer Science (CSE) 2008

The performance of a pipelined processor suffers if

  • A. the pipeline stages have different delays
  • B. consecutive instructions are dependent on each other
  • C. the pipeline stages share hardware resources
  • D. All of the above

Answer: D. All of the above

Explanation: Pipeline hazards include structural hazards (resource sharing), data hazards (dependencies), and bottlenecking from unequal stage delays.

| | All questions of ISRO Computer Science (CSE) 2008